Modeling of solder joint defects through a level-set approach
Myungjoo Kang 1, Susant K. Patra 21 Department of Mathematical Sciences, Seoul National University, Seoul, Korea
2 Department of Electrical and Computer Engineering, University of California, San diego, La Jolla, CA 92903, USA
Received by the editors January 8, 2007 and, in revised form, March 22, 2007
Due to the inherent nature of flip-chip assembly, the solder joints lie beneath the device and therefore are not amenable to visual inspection. Hence, it is important at the design stage to ensure that solder defects such as joint separation or joint shortening do not occur in the assembly. As a first step, the solder joint is modeled using a level-set approach. Unlike conventional front-tracking approaches, the levelset method handles complicated profiles arising from merger/separation of solder joints naturally without user intervention. The model was established to determine the upper and lower limit on optimal solder volume as a function of a specific assembly configuration and is used to avoid such defects.
AMS subject classifications: 35Q80, 65K10, 65M06
Key words: levelset; solder-joint; flip-chip
Email: email@example.com (M. Kang), firstname.lastname@example.org (S. K. Patra)