TY - JOUR
T1 - Modeling of Solder Joint Defects Through a Level-Set Approach
JO - International Journal of Numerical Analysis and Modeling
VL - 2
SP - 255
EP - 269
PY - 2008
DA - 2008/05
SN - 5
DO - http://doi.org/
UR - https://global-sci.org/intro/article_detail/ijnam/810.html
KW - levelset, solder-joint, flip-chip.
AB - <p style="text-align: justify;">Due to the inherent nature of flip-chip assembly, the solder
joints lie beneath the device and therefore are not amenable to visual
inspection. Hence, it is important at the design stage to ensure that
solder defects such as joint separation or joint shortening do not occur
in the assembly. As a first step, the solder joint is modeled using a
level-set approach. Unlike conventional front-tracking approaches, the
levelset method handles complicated profiles arising from
merger/separation of solder joints naturally without user intervention.
The model was established to determine the upper and lower limit on
optimal solder volume as a function of a specific assembly configuration
and is used to avoid such defects.</p>